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FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing

Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda and Koyo Nitta

NTT Device Innovation Center, NTT Corporation, Kanagawa, Japan


Network microbursts, which are sub-millisecond order bursts of traffic, have gathered attention due to causing network delay and packet loss. However, there are two problems in analyzing the causes of microbursts: how to capture the packet included in the microburst and how to specify the flows causing microbursts. To resolve these problems, we propose a field-programmable gate array (FPGA)-based microburst analysis system. This system detects microbursts with dedicated hardware in sub-millisecond time resolution. It can capture only packets before and after microburst detection triggered by detection with a static threshold for whole traffic. In addition, it can specify the flows causing microbursts by detection with a dynamic threshold for each flow. The experimental results show that the proposed system can capture only packets before and after microburst detection and can correctly specify the flow causing microbursts even in a network with fluctuating bandwidth usage in practical traffic conditions on the basis of network trace data in a datacenter. The proposed system is implemented with Intel® PAC with Arria® 10 GX FPGA and consumes relatively small amounts of hardware resources: 51% ALMs, 16% registers, and 57% block memories.


[The authors opted for not publicly sharing a presentation video.]

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