ASAP2020 Program of Events

To accommodate different time zones, the ASAP live events will run on two days for 5 hours per day starting each day at 15:00 UK time (=7:00 San-Francisco =22:00 Beijing) with a keynote.
Registered users can access presentation videos and papers and leave comments (just follow the paper links below).
During the technical live sessions, short teaser presentations will precede paper discussions.

Monday, July 6, 2020

15:00	Opening
15:15	Keynote I: "An Overview of High Performance computing and Using Mixed Precision in Numerical Computations to Speedup Linear Algebra Solvers" Jack Dongarra; University of Tennessee, USA and Oak Ridge National Laboratory, USA, and University of Manchester
16:00	Short Break
16:05-16:50	Session 1: "Heterogeneous Computing, Manycore Systems, Reconfigurable Accelerators" Chair: Ray Cheung, City University of Hong Kong • A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures Artur Podobas1,2, Kentaro Sano 1 and Satoshi Matsuoka1,3 1 RIKEN Center for Computational Science (R-CCS), Kobe, Japan 2 KTH Royal Institute of Technology, Stockholm, Sweden 3 Tokyo Institute of Technology, Japan • Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation Ryohei Kobayashi, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe and Masayuki Umemura University of Tsukuba, Japan • Termination detection for fine-grained message-passing architectures Matthew Naylor1, Simon W. Moore1, Andrey Mokhov2, David Thomas3, Jonathan R. Beaumont3, Shane Fleming4, A. Theodore Markettos1, Thomas Bytheway1 and Andrew Brown5 1 University of Cambridge, UK 2 Newcastle University and Jane Street, UK 3 Imperial College London, UK 4 Microsoft Research, UK 5 University of Southampton, UK • Condensing an overload of parallel computing ingredients into a single architecture recipe Riadh Ben Abdelhamid, Yoshiki Yamguchi and Taisuke Boku University of Tsukuba, Japan • FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda and Koyo Nitta NTT Device Innovation Center, NTT Corporation, Kanagawa, Japan • FPGA-Accelerated Time Series Mining on Low-Power IoT Devices Seongyoung Kang1, Jinyeong Moon2 and Sang-Woo Jun3 1 Kookmin University, Seoul, South Korea 2 Florida State University, Tallahassee, USA 3 University of California, Irvine, USA
16:50	Long Break
17:30-18:30	Session 2: "Machine Learning and Acceleration of Neural Networks" Guy Lemieux, Univeity of British Columbia, CA • Array Aware Training/Pruning: Methods for Efficient Forward Propagation on Array-based Neural Network Accelerators Krishna Teja Chitty-Venkata and Arun K. Somani Iowa State University, Ames, USA • Design Space Exploration for Softmax Implementations Zhigang Wei, Aman Arora, Pragenesh Patel and Lizy John The University of Texas at Austin, USA • Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier Blocks Aman Arora, Zhigang Wei and Lizy K. John The University of Texas at Austin, USA • Hardware Acceleration of Large Scale GCN Inference Bingyi Zhang, Hanqing Zeng and Viktor Prasanna University of Southern California, Los Angeles, USA • Training Neural Nets using only an Approximate Tableless LNS ALU Mark Arnold1, Ed Chester2 and Corey Johnson1 1 XLNS Research, USA 2 Goonhilly Earth Station, UK • Temporal Motionless Analysis of Video using CNN in MPSoC Somdip Dey1, Amit Kumar Sing1, Dilip Kumar Prasad2 and Klaus McDonald-Maier1 1 University of Essex, UK 2 UiT The Arctic University of Norway, Tromsø¸, Norway • An Efficient Convolution Engine based on the A-trous Spatial Pyramid Pooling Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello and Stefania Perri University of Calabria, Rende, Italy • Fast and Accurate Training of Ensemble Models with FPGA-based Switch Jiuxi Meng, Ce Guo, Nadeen Gebara and Wayne Luk Imperial College London, UK
18:30	Break
18:50-19:40	Session 3: "Emerging Technologies and Neuromorphic Computing" Chair: Nguyen Dao, The University of Manchester • Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System Dawen Xu1,2, Ziyang Zhu1,2, Cheng Liu1, Ying Wang1, Huawei Li1, Lei Zhang1 and Kwang-Ting Cheng3 1 Chinese Academy of Sciences, Beijing, China 2 Hefei University of Technology, China 3 Hong Kong University of Science and Technology, Hong Kong • A Parallel-friendly Majority Gate to Accelerate In-memory Computation John Reuben1 and Stefan Pechmann2 1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany 2 Universität Bayreuth, Germany • A System for Generating Non-Uniform Random Variates using Graphene Field-Effect Transistors Nathaniel J. Tye, James T. Meech, Bilgesu A. Bilgin and Phillip Stanley-Marbell University of Cambridge, UK • Efficient FeFET Crossbar Accelerator for Binary Neural Networks Taha Soliman1, Ricardo Olivo2, Tobias Kirchner1, Cecilia De la Parra1, Maximilian Lederer2, Thomas Kämpfe2, Andre Guntoro1 and Norbert Wehn3 1 Robert Bosch GmbH, Renningen, Germany 2 Fraunhofer IPMS, Center Nanoelectronic Technologies (CNT), Dresden, Germany 3 TU Kaiserslauten, Germany • A Design Methodology for Post-Moore's Law Accelerators: The Case of a Photonic Neuromorphic Processor Armin Mehrabian, Volker J. Sorger and Tarek El-Ghazawi The George Washington University, USA • Improved Side-Channel Resistance by Dynamic Fault-Injection Countermeasures Jan Richter-Brockmann1, Tim Güneysu1,2 1 Ruhr-Universität Bochum, Germany 2 DFKI, Germany
19:40	End of Day 1

Tuesday, July 7, 2020

15:00	Keynote II: "Formally Verifying Hardware for Secure and Private Computing” Satnam Singh, Software Engineer, Google Research
15:45-16:15	Session 4: "Computing in the Cloud and Datacenters" Nehir Sonmez, Barcelona Supercomputing Center • Architecture Support for FPGA Multi-tenancy in the Cloud Joel Mandebi Mbongue, Alex Shuping, Pankaj Bhowmik and Christophe Bobda University of Florida, Gainesville, USA • FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort Mikhail Asiatici1, Damian Maiorano2, and Paolo Ienne1 1 EPFL, Lausanne, Switzerland 2 Politecnico di Torino, Italy • SLATE: Managing Heterogeneous Cloud Functions Jessica Vandebon1, José G. F. Coutinho1, Wayne Luk1, Eriko Nurvitadhi2, and Mishali Naik2 1 Imperial College London, UK 2 Intel Corporation, San Jose, USA
16:15	Break
16:45-17:35	Session 5: "Approximate Computing and Computer Arithmetic" Chair: Christophe Bobda, University of Florida, Gainesville, USA • Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic Nuno Neves, Pedro Tomas and Nuno Roma Instituto Superior Tecnico Universidade de Lisboa, Portugal • Anytime Floating-Point Addition and Multiplication - Concepts and Implementations Marcel Brand1, Michael Witterauf1, Alberto Bosio2 and Jürgen Teich1 1 Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany 2 Ecole Centrale de Lyon, Institut des Nanotechnologies de Lyon, France • BWOLF: Bit-Width Optimization for Statistical Divergence with Logarithmic Functions Qian Xu, Guowei Sun and Gang Qu University of Maryland, College Park, USA • Efficient Floating-Point Implementation of the Probit Function on FPGAs (ASAP 2020 Best Paper) Mioara Joldes1 and Bogdan Pasca2 1 CNRS, LAAS, Toulouse, France 2 Intel Corporation, France ASAP 2020 Best Paper • Combining Fixed-Point and SORN Arithmetic in a MIMO BPSK-Symbol Detection Architecture Moritz Bärthel, Jochen Rust and Steffen Paul University of Bremen, Germany • ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation Mohammad Pivezhandi, Phillip H. Jones and Joseph Zambreno Iowa State University, Ames, USA
17:35	Break
17:50-18:25	Session 6: "Edge Computing" Chair: Xiaojun Zhai, University of Essex • Optimizing Grouped Convolutions on Edge Devices Perry Gibson1, José Cano1, Jack Turner2, Elliot J. Crowley2, Michael O'Boyle2 and Amos Storkey2 1 University of Glasgow, UK, 2 University of Edinburgh, UK • Dynamic Sharing in Multi-accelerators of Neural Networks on an FPGA Edge Device Hsin-Yu Ting, Tootiya Giyahchi, Ardalan Amiri Sani and Eli Bozorgzadeh University of California, Irvine, USA • A New Hardware Approach to Self-Organizing Maps Leonardo A. Dias1, Maria G. F. Coutinho1, Elena Gaura2 and Marcelo A. C. Fernandes1 1 Federal University of Rio Grande do Norte, Natal, Brazil 2 Coventry University, UK • Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection Johnson Loh, Jianan Wen and Tobias Gemmeke RWTH Aachen University, Germany
18:25	Closing ASAP 2020 Best Paper, ASAP 2021
18:40	After-ASAP Drink Have your favorite drink ready for a video toast.